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A highly stable SRAM memory cell with top-gated P--N drain poly-Si TFTs for 1.5V operation
被引：27
作者：
Hayashi, F
Ohkubo, H
Takahashi, T
Horiba, S
Noda, K
Uchida, T
Shimizu, T
Sugawara, N
Kumashiro, S
机构：
来源：
IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996
|
1996年
关键词：
D O I：
10.1109/IEDM.1996.553585
中图分类号：
TM [电工技术];
TN [电子技术、通信技术];
学科分类号：
0808 ;
0809 ;
摘要：
A novel memory cell has been proposed for low voltage operated, high speed and high density SRAMs. Features of this cell are (1) high performance poly-Si TFT loads utilizing bipolar action positively, and (2) a node contact structure which keeps current driveability of TFTs to the cell nodes high by the elimination of parasitic high resistance regions. The minimum operation voltage of 1.5 V has been confirmed by 0.3 micrometer design rule 64 kbit SRAMs without a boosted word-line scheme.
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页码：283 / 286
页数：4
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