A novel BST storage capacitor node technology using platinum electrodes for Gbit DRAMs

被引：20

作者：

Khamankar, RB ^{[1
]}

Kressley, MA ^{[1
]}

Visokay, MR ^{[1
]}

Moise, T ^{[1
]}

Xing, G ^{[1
]}

Nemoto, S ^{[1
]}

Okuno, Y ^{[1
]}

Fang, SJ ^{[1
]}

Wilson, AM ^{[1
]}

Gaynor, JF ^{[1
]}

Hurd, TQ ^{[1
]}

Crenshaw, DL ^{[1
]}

Summerfelt, S ^{[1
]}

Colombo, L ^{[1
]}

机构：

[1] Texas Instruments Inc, Dallas, TX 75265 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650372

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new stack capacitor structure using barium strontium titanate (BST) has been developed for Gbit scale DRAMs. The feasibility of fabrication of this structure using Pt as the electrode material is demonstrated through the use of novel processes. An appropriately placed oxidation resistant barrier and adhesion layers enhance the thermal and physical stability of the bottom electrode structure. Electrical results, including AC electrical stress reliability measurements, for 3-D storage nodes with side-wall contribution are presented. Fence-free etching of Pt for bottom electrode formation is shown using a new hard-mask based process. Successful back-end integration (ILD and metallization) of BST capacitors is also demonstrated.

引用

页码：245 / 248

页数：4