Bit vector architecture for computational mathematical morphology

被引:5
作者
Handley, JC [1 ]
机构
[1] Xerox Corp, Webster, NY 14580 USA
关键词
electronic printing; image processing hardware; increasing operators; lattice operators; nonlinear filters;
D O I
10.1109/TIP.2002.807362
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
A real-time, compact architecture is presented for translation-invariant windowed nonlinear discrete operators represented in computational mathematical morphology. The architecture enables output values to be computed in a fixed number of operations and thus can be pipelined. Memory requirements for an operator are proportional to its basis size. An operator is implemented by three steps: 1) each component of vector observation is used as an index into a table of bit vectors; 2) all retrieved bit vectors are "ANDed" together; and 3) the position of the first nonzero bit is used as an index to a table of output values. Computational mathematical morphology is described, the new architecture is illustrated through examples, and formal proofs are given. A modification of the basic architecture provides for increasing operators.
引用
收藏
页码:153 / 158
页数:6
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