Characterizing Jitter Performance of Multi Gigabit FPGA-Embedded Serial Transceivers

被引：17

作者：

Aloisio, Alberto ^{[1
,2
]}

Cevenini, Francesco ^{[1
,2
]}

Giordano, Raffaele ^{[1
,2
]}

Izzo, Vincenzo ^{[1
]}

机构：

[1] Ist Nazl Fis Nucl, Sez Napoli, I-80126 Naples, Italy

[2] Univ Naples Federico 2, Dipartimento Sci Fis, I-80126 Naples, Italy

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2010年 / 57卷 / 02期

关键词：

FPGAs; jitter; recovered clock; serial links; LHC DETECTORS;

D O I：

10.1109/TNS.2009.2032291

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

High-speed serial links are a key component of data acquisition systems for High Energy Physics. They carry physics events data and often also clock, trigger and fast control signals. For the latter applications, the jitter on the clock recovered from the serial stream is a critical parameter since it directly affects the timing performance of data acquisition and trigger systems. Latest Field Programmable Gate Arrays (FPGAs) include multi-gigabit serial transceivers, which are configurable with various options and support many data encodings. However, an in-depth jitter characterization of those devices is not available yet. In this paper we present measurements of the jitter on the clock recovered by a GTP transceiver (embedded in a Xilinx Virtex 5 FPGA) as a function of the data pattern, coding and logic activity on the transmitter and receiver FPGAs.

引用

页码：451 / 455

页数：5