Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance

被引:51
作者
Underwood, KD [1 ]
Hemmert, KS [1 ]
机构
[1] Sandia Natl Labs, Albuquerque, NM 87185 USA
来源
12TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS | 2004年
关键词
IEEE floating point; arithmetic; FPGA; reconfigurable computing;
D O I
10.1109/FCCM.2004.21
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Field programmable gate arrays (FPGAs) have long been an attractive alternative to microprocessors for computing tasks - as long as floating-point arithmetic is not required. Fueled by the advance of Moore's Law, FPGAs are rapidly reaching sufficient densities to enhance peak floating-point performance as well. The question, however is how much of this peak performance can be sustained. This paper examines three of the basic linear algebra subroutine (BLAS) functions: vector dot product, matrix-vector multiply, and matrix multiply. A comparison of microprocessors, FPGAs, and Reconfigurable Computing platforms is performed for each operation. The analysis highlights the amount of memory bandwidth and internal storage needed to sustain peak performance with FPGAs. This analysis considers the historical context of the last six years and is extrapolated for the next six years.
引用
收藏
页码:219 / 228
页数:10
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