Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process

A broad range of high-volume consumer applications require low-power, battery operated, wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost and versatility. The design of such systems highlights many tradeoffs between performances, lifetime, cost and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1V). These considerations are illustrated by design examples taken from a transceiver chip realized in a standard 0.5 square m digital CMOS process. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit prototype operates in the 434 MHz ISM band and consumes only 1mW in receive mode. It achieves a -95dBm sensitivity for a data rate of 24kbit/s. The transmitter section is designed for OdBm output power under the minimum 1V supply, with a global efficiency higher than 15%.