Planarized multilevel interconnection using chemical mechanical polishing of selective CVD-Al via plugs

被引：11

作者：

Amazawa, T ^{[1
]}

Yamamoto, E ^{[1
]}

Arita, Y ^{[1
]}

机构：

[1] NTT, Syst Elect Labs, Kanagawa 24301, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1998年 / 45卷 / 04期

关键词：

aluminum integrated circuit conductors; aluminum materials/devices; CVD; electromigration; integrated circuit metallization; interconnections; CMP;

D O I：

10.1109/16.662782

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A planarization process for selective CVD-AI via plugs using chemical mechanical polishing (CMP) is proposed and a four-level interconnection system with all stacked via plugs is demonstrated, A Cl-2/Ar post-cleaning treatment after Al plug CMP is shown to be the key process in obtaining excellent via chain characteristics with high yield and small resistance scattering, A sandwich of Ti/TiN/Ti barrier layers with a CVD-AI plug is proved to be one of the best via plug structures because of its low via resistance and high reliability, Quarter-micron 120-kG gate array LSI's have been successfully fabricated using a 1.3-mu m, equal pitch and four-level interconnection.

引用

页码：815 / 820

页数：6

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