Fmax enhancement of dynamic threshold-voltage MOSFET (DTMOS) under ultra-low supply voltage

被引:20
作者
Tanaka, T [1 ]
Momiyama, Y [1 ]
Sugii, T [1 ]
机构
[1] Fujitsu Labs Ltd, Atsugi, Kanagawa 24301, Japan
来源
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年
关键词
D O I
10.1109/IEDM.1997.650415
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The high frequency characteristics of DTMOS is described here for the first time. Our DTMOS has a small parasitic resistance due to an optimized Co salicide technology and a small parasitic capacitance due to a reduction in the overlapped region between the gate and drain, which is achieved by gate poly-Si oxidation before LDD implantation. We obtained an Ft of 78 GHz and an Fmax of 37 GHz for a 0.1 mu m-Leff DTMOS even at a supply voltage of 0.7 V. We also noted an Fmax enhancement of 1.5 times compared to that of a conventional SOI MOSFET, which is attributed to a high transconductance and a large output resistance.
引用
收藏
页码:423 / 426
页数:4
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