Low resistance Ti or Co salicided raised source drain transistors for sub-0.13μm CMOS technologies

被引：25

作者：

Chao, CP ^{[1
]}

Violette, KE ^{[1
]}

Unnikrishnan, S ^{[1
]}

Nandakumar, M ^{[1
]}

Wise, RL ^{[1
]}

Kittl, JA ^{[1
]}

Hong, QZ ^{[1
]}

Chen, IC ^{[1
]}

机构：

[1] Texas Instruments Inc, Semicond Proc & Device Ctr, Dallas, TX 75265 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.649474

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Raised source/drain (R/SD) CMOS transistors with Co or Ti salicide to improve narrow-poly sheet resistance and diode leakage are studied. At 0.11 mu m gate length, low resistance of 2 Ohm/sq and 1.2 Ohm/sq are achieved for CoSi2 (with 400 Angstrom R/SD) and TiSi2 with 700 Angstrom R/SD and preamorphization implant (PAI), respectively. These results are due to the lateral over-growth of the deposited silicon to form T-shaped gates. Significant improvement in the junction leakage current is also observed for the R/SD devices with CoSi2 salicide. Comparison of integration issues such as silicide bridging, poly depletion, and gate oxide integrity are presented together with transistor drive current and source/drain series resistance.

引用

页码：103 / 106

页数：4