Limits of gate-oxide scaling in nano-transistors

被引:62
作者
Yu, B [1 ]
Wang, HH [1 ]
Riccobene, C [1 ]
Xiang, Q [1 ]
Lin, MR [1 ]
机构
[1] Adv Micro Devices Inc, Sunnyvale, CA 94088 USA
来源
2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年
关键词
D O I
10.1109/VLSIT.2000.852781
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper explores the ultimate scaling limit of gate oxide due to MOSFET gate leakage and device performance. The limit on Tox reduction with respect to gate leakage tolerance is considered by the concept of "dynamic" gate leakage in nano-scale MOSFET's. Tox scaling is also limited by transistor performance degradation due to the loss of inversion layer charge through gate leakage and the degradation of carrier mobility in the channel from increased scattering. All the three effects are investigated experimentally on CMOS devices with gate length down to 50nm and gate Tox down to 12 Angstrom. The minimum Tox is proposed and the implications on voltage scaling, high-k gate dielectrics and low-temperature CMOS are discussed.
引用
收藏
页码:90 / 91
页数:2
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