Noise margins of threshold logic gates containing resonant tunneling diodes

被引：1

作者：

Bhattacharya, M ^{[1
]}

Mazumder, P ^{[1
]}

机构：

[1] Univ Michigan, Dept Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA

来源：

PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI | 1998年

关键词：

D O I：

10.1109/GLSV.1998.665201

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Threshold gates consisting of RTDs in conjunction with HBTs or CHFETs or MOS transistors can form extremely compact, ultrafast, digital logic alternatives. The resonant tunneling phenomenon causes these circuits to exhibit super-high-speed switching capabilities. Additionally, by virtue of being threshold logic gates, they are guaranteed to be more compact than traditional digital logic circuits while achieving the same functionality. However, reliable logic design with these gates will need a thorough understanding of their noise performance and pourer dissipation among other things. In this paper, we present an analytical study of the noise performance of these threshold gates supplemented by computer simulation results, with the objective of obtaining reliable circuit design guidelines.

引用

页码：65 / 70

页数：6