Resizing rules for the reuse of MOS analog designs

被引：6

作者：

Montoro, CG ^{[1
]}

Schneider, MC ^{[1
]}

机构：

[1] Univ Fed Santa Catarina, BR-88040900 Florianopolis, SC, Brazil

来源：

13TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/SBCCI.2000.876013

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a redesign procedure for analog circuits based on a scalable model of the MOSFET. A set of very simple expressions allows the calculation of transistor dimensions and bias for a given circuit in a new generation technology, starting from the circuit designed in an earlier technology.

引用

页码：89 / 93

页数：5

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