CMOS DLL based 2V, 3.2ps jitter, 1GHz clock synthesizer and temperature compensated tunable oscillator.

被引：12

作者：

Foley, DJ ^{[1
]}

Flynn, MP ^{[1
]}

机构：

[1] Univ Coll Cork, NMRC, Cork, Ireland

来源：

PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2000年

关键词：

D O I：

10.1109/CICC.2000.852688

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator. Both of these circuits employ a self-correcting Delay Locked Loop (DLL). The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer and provides temperature compensated biasing for the tunable oscillator. With a 2V supply the measured RMS jitter for the 1GHz synthesizer output was 3.2ps. With a 3.3V supply RMS jitter of 3.1ps was measured for a 1.6GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0 to 85 degrees C. The circuits were fabricated on a generic 0.5 mu m digital CMOS process.

引用

页码：371 / 374

页数：4