Experimental and simulation studies of single-electron-transistor-based multiple-valued logic

被引：17

作者：

Inokawa, H ^{[1
]}

Takahashi, Y ^{[1
]}

机构：

[1] NTT Corp, NTT Basic Res Labs, Atsugi, Kanagawa 2430198, Japan

来源：

33RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/ISMVL.2003.1201415

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Periodic drain current-gate voltage characteristics of single-electron transistors (SETs) were utilized to construct basic components of multiple-valued logic (MVL), such as a universal literal gate and a quantizer. In order to supplement the small gain and the small applicable voltage of the SET, hybrid SET-MOSFET scheme is proposed and demonstrated experimentally using CMOS-compatible pattern-dependent oxidation (PADOX) technology. We also succeeded in reproducing the results using a SPICE circuit simulator with a compact analytical SET model, and estimated the performance of the proposed MVL.

引用

页码：259 / 266

页数：8

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