16Mb DRAM/SOI technologies for sub-1V operation

被引：12

作者：

Oashi, T

Eimori, T

Morishita, F

Iwamatsu, T

Yamaguchi, Y

Okuda, F

Shimomura, K

Shimano, H

Sakashita, N

Arimoto, K

Inoue, Y

Komori, S

Inuishi, M

Nishimura, T

Miyoshi, H

机构：

来源：

IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996 | 1996年

关键词：

D O I：

10.1109/IEDM.1996.554057

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET's, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1V.

引用

页码：609 / 612

页数：4