Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation

被引：98

作者：

Takeuchi, K ^{[1
]}

Tatsumi, T ^{[1
]}

Furukawa, A ^{[1
]}

机构：

[1] NEC, Silicon Syst Res Labs, Kanagawa 229, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650512

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A simple model is proposed, which is able to calculate V-TH Standard deviation due to random dopant placement in the channel, for arbitrary vertical impurity distributions. Substantial decrease in V-TH fluctuation, while keeping V-TH the same, is confirmed for low surface impurity channel MOSFETs, in agreement with the model prediction.

引用

页码：841 / 844

页数：4