Three dimensional through-wafer fan-out optical interconnects

As processor speeds rapidly approach the Gigahertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processor performance. In addition, limitations in interconnect density and bandwidth serve to exacerbate current bottlenecks, particularly as computer architectures continue to reduce in size. To address these issues, we propose a 3D architecture based on through-wafer vertical optical interconnects. To facilitate integration into the current manufacturing infrastructure, our system is monolithically fabricated in the Silicon substrate and preserves scale of integration by using meso-scopic diffractive optical elements (DOEs) for beam fan-out. We believe that this architecture can alleviate the disparity between processor speeds and memory access times while increasing interconnect density by at least an order of magnitude. We are currently working to demonstrate a prototype system that consists of vertical cavity surface emitting lasers (VCSELs), diffractive optical elements, photodetectors, and memory units integrated on a single silicon substrate. To this end, we are currently refining our fabrication and analysis methods for the realization of meso-scopic DOEs. In this paper, we present our progress to date and demonstrate through-Silicon optical data transmission using DOEs that were designed, fabricated, and characterized at the University of Delaware. We present the validation of our theoretical models for the design of such DOEs with experimental data and discuss applications for our proposed architecture including instruction level parallel processors (ILPs) and field programmable gate arrays (FPGAs).