STI process steps for sub-quarter micron CMOS

被引：20

作者：

Sallagoity, P

Gaillard, F

Rivoire, M

Paoli, M

Haond, M

McClathie, S

机构：

[1] France Telecom, Ctr Natl Etud Telecommun, F-38243 Meylan, France

[2] Electrotech, Thornbury Labs, Bristol BS12 1NP, Avon, England

来源：

MICROELECTRONICS RELIABILITY | 1998年 / 38卷 / 02期

关键词：

D O I：

10.1016/S0026-2714(97)00166-2

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents Shallow Trench Isolation (STI) process steps for sub-1/4 mu m CMOS technologies. Dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection, have been used for a 0.18 mu m CMOS technology. Electrical results obtained with a 5.5 nm gate oxide thickness show good isolation down to 0.3 mu m spacing. Good transistor performances have been demonstrated. (C) 1998 Published by Elsevier Science Ltd.

引用

页码：271 / 276

页数：6

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