A novel 0.25 mu m shallow trench isolation technology

A novel shallow trench isolation technology has been proposed for 0.25 mu m CMOS VLSI applications. The gate oxide and a thin poly layer are processed first, followed by the shallow trench isolation, channel and high-energy well The subthreshold conduction shallow trench isolated MOSFET's, as so called ''kink effect'' due to field crowding at active edge, has been successfully eliminated. No inverse narrow width effect is observed. The inter-well isolation, N+/P+ spacing, is shrinkable down to 0.8 mu m for 0.25 mu m CMOS technology. Well behaved 0.25 mu m MOSFET's with off-state leakage less than 1 pA/mu m, were obtained at 2.5 V supply voltage. This isolation technology has also been integrated into 0.25 mu m high-performance logic and high-density SRAM circuits.