A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems

被引:77
作者
Costas-Santos, Jesus [1 ]
Serrano-Gotarredona, Teresa
Serrano-Gotarredona, Rafael
Linares-Barranco, Bernabe
机构
[1] CSIC, IMSE, CNM, Seville 41012, Spain
[2] Spanish Minist Educ & Sci, Seville, Spain
[3] NXP Philipps Semicond, A-1801 Graz, Austria
关键词
address-event representation (AER); analog circuits; artifical retina; calibration; contrast computation; current-mode; circuits imagers; low-power circuits and systems; mismatch; neuromorphic circuits; sensory systems; trimming; vision systems; weak inversion circuits; OPTIC-NERVE SIGNALS; COMMUNICATION; SENSOR; ARCHITECTURE; NETWORKS; CAMERA;
D O I
10.1109/TCSI.2007.900179
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present a 32 x 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring,pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 mu m x 56 mu m, while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35-mu m CMOS process.
引用
收藏
页码:1444 / 1458
页数:15
相关论文
共 73 条
[1]  
ABRAHAMSEN J, 2004, P IEEE INT S CIRC SY, V5, P361
[2]  
ANDREOU A, 1994, WORKSH PHYS COMP PHY, P255
[3]  
Andreou A. G., 1995, Proceedings. Sixteenth Conference on Advanced Research in VLSI, P225, DOI 10.1109/ARVLSI.1995.515623
[4]  
Andreou A. G., 1991, ADV NEURAL INFORMATI, P764
[5]   Translinear circuits in subthreshold MOS [J].
Andreou, AG ;
Boahen, KA .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1996, 9 (02) :141-166
[6]  
[Anonymous], ADV NEURAL INFORM PR
[7]  
[Anonymous], 1989, ANALOG VLSI NEURAL S
[8]  
[Anonymous], 1999, Pulsed Neural Networks
[9]   Motion vision sensor architecture with asynchronous self-signaling pixels [J].
AriasEstrada, M ;
Poussart, D ;
Tremblay, M .
CAMP'97 - FOURTH IEEE INTERNATIONAL WORKSHOP ON COMPUTER ARCHITECTURE FOR MACHINE PERCEPTION, PROCEEDINGS, 1997, :75-83
[10]   A 100 x 100 pixel silicon retina for gradient extraction with steering filter capabilities and temporal output coding [J].
Barbaro, M ;
Burgi, PY ;
Mortara, A ;
Nussbaum, P ;
Heitger, F .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (02) :160-172