Deep-trap SILC (stress induced leakage current) model for nominal and weak oxides

被引:36
作者
Kamohara, S [1 ]
Park, DG [1 ]
Hu, CM [1 ]
机构
[1] Hitachi Ltd, Cent Res Lab, Semicond & Integrated Circuit Div, Kokubunji, Tokyo 185, Japan
来源
1998 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 36TH ANNUAL | 1998年
关键词
D O I
10.1109/RELPHY.1998.670443
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We have successfully developed a new quantitative ITAT (inelastic trap-assisted tunneling)-based SILC (stress induce leakage current) model by introducing traps with a deep energy level of around 4.0eV which can explain both of the two field dependencies, i.e. Fowler-Nordheim (FN)-field and the direct tunneling (DT) -field dependence. For simple analytical models, we introduce the most favorable trap position, which gives the largest contribution to the leakage current. A-mode and B-mode SILC are the leakage currents in the nominal oxide region and at the weak oxide spots, respectively, which can be deduced by the large difference of the area density between the single trap area (similar to 1E11 cm(-2)) and the multi-trap path (similar to 1E2 cm(-2)). Our model suggests that for flash EPROM a 13nm-oxide thickness is required for 1.0 fC on the floating gate to last 100 years.
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页码:57 / 61
页数:5
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