Optimal structure of Wafer Level Package for the electrical performance

RDD, which is being regarded as a next generation main memory, has very high data transfer rate up to several hundred MHz. In order to satisfy the electrical requirement at high speeds, CSP-type packages are adopted, in general. Recently, WLP (Wafer Level Package) has been proposed as a candidate for RDD package because of their low manufacturing cost. Because of the extreme close distance between the metal trace and silicon on a WLP, the electrical requirements of RDD cannot be easily satisfied. In order to satisfy the electrical requirements for RDD including Ci, design factors of WLP such as redistributed pattern design, materials, and structure of dielectric inter-layer should be optimized. This paper describes the evaluation of WLP as a RDD package with respect to electrical performance and proposes an optimal structure for the WLP. Various WLP types were also analyzed in electrical perspective. The electrical characteristics of WLP was estimated and analyzed by using a proposed structure of dielectric inter-layer through electro-magnetic simulation and comparing actual measurement data. The optimal design parameters of WLP are also proposed to ensure electrical performance.