An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS

被引：93

作者：

Stonick, JT ^{[1
]}

Wei, GY

Sonntag, JL

Weinlader, DK

机构：

[1] Accelerant Networks Inc, Beaverton, OR 97006 USA

[2] Harvard Univ, Cambridge, MA 02138 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 03期

关键词：

adaptive equalization; backplane transceiver; CMOS; equalization; high-speed links; multilevel signaling; preemphasis; pulse amplitude modulation (PAM); transceiver;

D O I：

10.1109/JSSC.2002.808282

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The 17-mm(2) device is implemented in a 0.25-mum CMOS process, operates off of 2.5- and 3.3-V supply voltages, and consumes 1 W.

引用

页码：436 / 443

页数：8

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[3]

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[4]

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[5]

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[6]

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[7]

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