An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield

被引：5

作者：

Noda, K ^{[1
]}

Matsui, K ^{[1
]}

Ito, S ^{[1
]}

Masuoka, S ^{[1
]}

Kawamoto, H ^{[1
]}

Ikezawa, N ^{[1
]}

Takeda, K ^{[1
]}

Aimoto, Y ^{[1
]}

Nakamura, N ^{[1
]}

Toyoshima, H ^{[1
]}

Iwasaki, T ^{[1
]}

Horiuchi, T ^{[1
]}

机构：

[1] NEC Corp Ltd, ULSI Device Dev Lab, Sagamihara, Kanagawa 2291198, Japan

来源：

PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2000年

关键词：

D O I：

10.1109/CICC.2000.852667

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We have developed two schemes for improving access speed and reliability of a loadless four-transistor (4T) SRAM cell: a dual-layered twisted bit line, which reduces coupling capacitance between adjacent bit lines in order to achieve high-speed read/write operations; and triple-well shielding, which protects the memory cell from substrate noise and alpha particles. We incorporated these technologies in a 0.18-mu m CMOS process and fabricated a 16-Mb SRAM macro with a 1.9-mu m(2) memory cell. This macro fully functions at 400 MHz and has an access time of 2.35 ns.

引用

页码：283 / 286

页数：4