Tolerance-based process proximity correction (PPC) verification methodology

被引：7

作者：

Hashimoto, K ^{[1
]}

Fujise, H ^{[1
]}

Nojima, S ^{[1
]}

Ito, T ^{[1
]}

Ikeda, T ^{[1
]}

机构：

[1] Toshiba Co Ltd, Semicond Co, Proc & Mfg Engn Ctr, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

PHOTOMASK AND NEXT GENERATION LITHOGRAPHY MASK TECHNOLOGY XI | 2004年 / 5446卷

关键词：

tandem process proximity correction (PPC); pattern feature extraction; tolerance-based PPC verification; process proximity effect (PPE);

D O I：

10.1117/12.557795

中图分类号：

O43 [光学];

学科分类号：

070207 ; 0803 ;

摘要：

Tolerance-based process proximity correction (PPC) verification methodology is proposed for "hot spot management" in LSI fabrication process flow. This methodology verifies the PPC accuracy with the features of actual processed wafers/masks and target features in CAD data including CD tolerance around hot spots. The CD tolerance in CAD data is decided according to device characteristics, process integration, CD budget, and so on, and is used for the judgment criteria of the PPC accuracy. After the verifications, the actions in the manufacturing are decided. This methodology is demonstrated for the 65nm-node CMOS local metal at three representative hot spots extracted by lithography simulation, and the results yielded useful information for the manufacturing.

引用

页码：471 / 480

页数：10

共 7 条

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