Bias stress in pentacene transistors measured by four probe transistor structures

This paper deals with operational lifetime measurements of organic field-effect transistors. The organic semiconductor under study is pentacene, the gate dielectric is thermal SiO2, treated with an OTS self-assembled monolayer and the source and drain electrodes are gold, treated with thiols. The source and drain are defined by photolithography, and the channel length is 100 microns. We apply DC stress conditions on these structures, and monitor the output characteristics of the TFTs during stress as well as during recovery after stress. The transistor structures have been modified to incorporate two voltage-measurement probes in the channel in addition to the source and drain contacts. This results in a 4-probe configuration, that allows to measure the voltage drop in the intrinsic transistor channel separately from the voltage drop over the source and the drain contact regions. When applying a constant (DC) gate-source bias (V-GS) corresponding to a field in the gate insulator of 1 MV/cm, we observe two degradation mechanisms: one part of the degradation is permanent, the other part recovers. The permanent degradation could be traced back to the drain side. It typically results in the current halving after 2 hours of stress at a vertical (gate insulator) field of 1 MV/cm. The degradation measured during stress includes both this permanent degradation and the recoverable part. It is significantly larger in magnitude than the permanent degradation, resulting in typically a factor of 10 or more in drain current. The magnitude of the recoverable degradation not only depends on the gate voltage, but also on the drain voltage. It is therefore a consequence of the lateral field at the drain side of the channel. This phenomenological study is a first step towards a comprehensive model for degradation of bias stress in organic field-effect transistors.