Thermomechanical finite element analysis of problems in electronic packaging using the disturbed state concept: Part 2 - Verification and application

被引：21

作者：

Basaran, C ^{[1
]}

Desai, CS

Kundu, T

机构：

[1] SUNY Buffalo, Dept Civil Engn, Buffalo, NY 14260 USA

[2] Univ Arizona, Dept Civil Engn & Engn Mech, Tucson, AZ 85718 USA

来源：

JOURNAL OF ELECTRONIC PACKAGING | 1998年 / 120卷 / 01期

关键词：

D O I：

10.1115/1.2792285

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The finite element procedure with the unified disturbed state modelling concept presented in Part I, Basaran et al. (1998), is verified here with respect to laboratory test results for Pb40/Sn60 eutectic solder alloy. This solder alloy is a commonly used interconnection material for surface mount technology packages. It is demonstrated that the proposed procedure provides highly satisfactory correlation with the observed laboratory behavior of materials and with test results for a chip-substrate system simulated in the laboratory.

引用

页码：48 / 53

页数：6

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