Address bus encoding techniques for system-level power optimization

被引：68

作者：

Benini, L ^{[1
]}

De Micheli, G ^{[1
]}

Macii, E ^{[1
]}

Sciuto, D ^{[1
]}

Silvano, C ^{[1
]}

机构：

[1] Politecn Milan, Dipartimento Elettr & Informaz, I-20133 Milan, Italy

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/DATE.1998.655959

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I/O interfaces can provide significant savings on the overall power budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, the schemes illustrated here target the reduction of the average number of bus line transitions per clock cycle. Experimental results, conducted on address streams generated by a real microprocessor, have demonstrated the effectiveness of the proposed methods.

引用

页码：861 / 866

页数：6