Atomic layer deposition of hafnium silicate gate dielectric layers

Downscaling equivalent oxide thickness (EOT) by decreasing the physical thickness or increasing the permittivity of the gate dielectric is required to reach the complementary metal-oxide semiconductor (CMOS) (sub) 45 nm node performance specifications. In this work, we study the atomic layer deposition (ALD) of hafnium silicate gate dielectrics from HfCl4, SiCl4, and H2O both experimentally and theoretically. Hafnium silicate is characterized by Rutherford backscattering, time-of-flight secondary ion mass spectroscopy, and x-ray photoelectron spectroscopy. The interaction of the precursors with the surface sites is investigated by first-principles calculations. The electrical properties are evaluated on TaN gated capacitors. The HfCl4/H2O reactions create surface sites that enable the chemisorption of SiCl4 in doses much smaller than the doses required for SiO2 ALD from SiCl4/H2O. The hydrolysis of Si-Cl is slower than the hydrolysis of Hf-Cl. Optimization of the hafnium silicate deposition results in a leakage current reduction of one order of magnitude for ultrascaled hafnium silicate gate stacks. At 0.9 nm EOT, a leakage current of <0.1 A/cm(2) is obtained for hafnium silicates with Hf content higher than 90%. (c) 2007 American Vacuum Society.