Impact of bottom interfacial layer on the threshold voltage and device reliability of fluorine incorporated pmosfets with high-K/metal gate

被引：8

作者：

Choi, Kisik ^{[1
]}

Lee, Taeho ^{[1
,2
]}

Barnett, Joel ^{[1
]}

Harris, Harlan R. ^{[1
,3
]}

Kweon, Seungsoo ^{[1
,2
]}

Young, Chadwin ^{[1
]}

Bersuker, Gennadi ^{[1
]}

Lee, Byoung Hun ^{[1
,4
]}

Jammy, Rajaro ^{[1
,4
]}

机构：

[1] SEMATECH, 2706 Montopolisi Dr, Austin, TX 78741 USA

[2] Univ Texas Austin, Austin, TX 78712 USA

[3] AMD Assignee, Sunnyvale, CA USA

[4] IBM Assignee, New York, NY USA

来源：

2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL | 2007年

关键词：

D O I：

10.1109/RELPHY.2007.369918

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The effect of F implantation combined with high quality bottom interfacial layer has been investigated in terms of threshold voltage reduction and improvement of device performance of TaCN/AlN/HfSiOx gate stacks for PMOS application. Threshold voltage becomes more positive as AlN, F implantation, and thermally grown interfacial layer steps are added. It is found that F accumulates near the interface with the Si substrate and the observed V-th shift has been attributed to the passivation of positively charged defects in the dielectric stack and additional negative charge associated with F atoms. Thermally grown interfacial layer combined with F implantation resulted in excellent device parameters and reliability as well as lower PMOS Vth due to inherently lower defect density and defect passivation effect by F atoms.

引用

页码：374 / +

页数：2