Reliability properties of low-voltage ferroelectric capacitors and memory arrays

被引：102

作者：

Rodriguez, JA ^{[1
]}

Remack, K

Boku, K

Udayakumar, KR

Aggarwal, S

Summerfelt, SR

Celii, FG

Martin, S

Hall, L

Taylor, K

Moise, T

McAdams, H

McPherson, J

Bailey, R

Fox, G

Depner, M

机构：

[1] Texas Instruments Inc, Dallas, TX 75243 USA

[2] Ramtron Int Corp, Colorado Springs, CO 80921 USA

来源：

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2004年 / 4卷 / 03期

关键词：

Bit distribution; fatigue; ferroelectric memory; FRAM; I-V; imprint; polarization; PZT; retention;

D O I：

10.1109/TDMR.2004.837210

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-mn CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-mn thick MOCVD PZT rerroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows similar to1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10(13) write/read polarization switching cycles. Retention measured after 10(12) switching cycles demonstrates no degradation relative to arrays with minimal cycling.

引用

收藏

页码：436 / 449

页数：14

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