A pulsed vision chip with inhibitory interconnections

被引：3

作者：

Ohta, J ^{[1
]}

Uehara, A ^{[1
]}

Tokuda, T ^{[1
]}

Nunoshita, M ^{[1
]}

机构：

[1] Nara Inst Sci & Technol, Grad Sch Mat Sci, Nara 6300101, Japan

来源：

OPTICS IN COMPUTING 2000 | 2000年 / 4089卷

关键词：

vision chips; pulse frequency modulation; CMOS image sensors;

D O I：

10.1117/12.386868

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper proposes and demonstrates a novel type of a vision chip that utilizes pulse trains for image processing. The chip is based on a pulse frequency modulation (PFM) technique, which is used in neurobiological systems. Two types of chips are designed;one is a pixel TEG (test element group) chip for testing availability of PFM for image acquisition using 0.35 mu m triple-metal double-poly CMOS process and the other is for a vision chip with inhibitory interconnections using 1.2 mu m double-metal double-poly CMOS process. The TEG chip works well in the power supply voltage of 0.7V and has a dynamic range of 20dB with a power consumption of less than 1 mu W. The operation of the mutual inhibition in the vision chip is confirmed by simulation. Also the comparison with the other pulse modulation technique, pulse width modulation is discussed.

引用

页码：488 / 495

页数：2

共 8 条

[1]

ANDOH F, 1999, IEEE WORKSH CHARG CO, P44

[2]

Koch C., 1995, VISION CHIPS IMPLEME

[3]

MASS W, 1998, PULSED NEURAL NETWOR

[4]

Mead C, 1989, ANALOG VLSI NEURAL S

[5]

NAGATA M, 1999, IEEE S VLSI CIRC, P141

[6] Histogram-equalization-based adaptive image sensor for real-time vision [J].

Ni, Y ;

Devos, F ;

Boujrad, M ;

Guan, JH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (07) :1027-1036

[7] Technology and device scaling considerations for CMOS imagers [J].

Wong, HS .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (12) :2131-2142

[8]

YANG W, 1994, IEEE INT SOL STAT CI, P230

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