A novel high-density 5F2 NAND STI cell technology suitable for 256Mbit and 1Gbit flash memories

被引：16

作者：

Shimizu, K ^{[1
]}

Narita, K ^{[1
]}

Watanabe, H ^{[1
]}

Kamiya, E ^{[1
]}

Takeuchi, Y ^{[1
]}

Yaegashi, T ^{[1
]}

Aritome, S ^{[1
]}

Watanabe, T ^{[1
]}

机构：

[1] Toshiba Corp, Microelect Engn Lab, Isogo Ku, Yokohama, Kanagawa 235, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650379

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a novel high density 5F(2) (F: feature size) NAND STI cell technology which has been developed for a low bit-cost flash memories. The extremely small cell size of 0.31um(2) has been obtained for the 0.25um design rule. To minimize the cell size, a floating gate is isolated with a shallow trench isolation(STI) and a slit formation by a novel SiN spacer process, which has made it possible to realize a 0.55um-pitch isolation at a 0.25um design rule. Another structural feature integral to the cell and its small size is tbe borderless bit-line and source-line contacts which are self-aligned with the select-gate. The proposed NAND cell with the gate length of 0.2um and the isolation space of 0.25um shows a normal operation as a transistor without any punch-through. Therefore, this 5F(2) NAND STI cell technology is essential to realize a low cost flash memories of 256Mbit and 1Gbit for mass-storage applications.

引用

页码：271 / 274

页数：4