Designing VRM hysteretic controllers for optimal transient response

This paper presents a design methodology for voltage hysteretic regulators powering digital integrated circuits with low voltage, high current, and high slew rate current transients. The design approach optimizes the transient response during large consumption changes by imposing constant closed-loop output impedance. This paper also suggests a novel compensator network for the adaptive voltage positioning feedback loop, which leads to a robust transient response performance against load disturbances. The application of the design methodology to the proposed hysteretic controller provides the suitable control parameter values for optimal transient response. Simulation and experimental results validate the theoretical predictions for the proposed controller, particularly the constant output impedance operation and the robust transient response performance.