CoSi2 with low diode leakage and low sheet resistance at 0.065μm gate length

被引：21

作者：

Hong, QZ ^{[1
]}

Shiau, WT ^{[1
]}

Yang, H ^{[1
]}

Kittl, JA ^{[1
]}

Chao, CP ^{[1
]}

Tsai, HL ^{[1
]}

Krishnan, S ^{[1
]}

Chen, IC ^{[1
]}

Havemann, RH ^{[1
]}

机构：

[1] Texas Instruments Inc, Semicond Proc & Device Ctr, Mat Sci Lab, Dallas, TX 75243 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.649475

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a comprehensive study of four diode leakage reduction methods, i.e. pre-metal deposition sputter clean, pre-metal deposition amorphization implant, high temperature silicidation, and high temperature metal deposition, for Co salicided junctions and their impact on sub-0.18 mu m CMOS device performance. The preferred methods are high temperature silicidation and/or high temperature Co deposition, which result in low diode leakage and little device degradation. CoSi2 formed by the low diode leakage processes can achieve a mean sheet resistance of similar to 6 ohm/sq. on N+ gates with gate lengths down to 0.065 mu m.

引用

页码：107 / 110

页数：4