Asynchronous macrocell interconnect using MARBLE

被引：12

作者：

Bainbridge, WJ ^{[1
]}

Furber, SB ^{[1
]}

机构：

[1] Univ Manchester, Dept Comp Sci, Manchester M13 9PL, Lancs, England

来源：

ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS - FOURTH INTERNATIONAL SYMPOSIUM | 1998年

关键词：

D O I：

10.1109/ASYNC.1998.666499

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper introduces MARBLE, the Manchester AsynchRonous Bus for Low Energy, a two channel micropipeline bus with centralized arbitration and address decoding which provides for the interconnection of asynchronous VLSI macrocells. In addition to basic bus functionality, MARBLE supports bus-bridging and test access, demonstrating that all the functions of a high speed macrocell bus can be implemented efficiently in a fully asynchronous design style. MARBLE is used in the AMULET3i microprocessor to connect the CPU core and DMA controller to RAM, ROM and peripherals. It exploits pipelining of the arbitration, address and data cycles, together with spatial locality optimizations and in-order split transfers, to supply the bandwidth requirements of such a system. The design of a MARBLE initiator data interface used in the AMULET3i is presented, including a Petri-net specification suitable for synthesis using the Petrify tool.

引用

页码：122 / 132

页数：11