A 90-nm logic technology featuring strained-silicon

被引:510
作者
Thompson, SE [1 ]
Armstrong, M [1 ]
Auth, C [1 ]
Alavi, M [1 ]
Buehler, M [1 ]
Chau, R [1 ]
Cea, S [1 ]
Ghani, T [1 ]
Glass, G [1 ]
Hoffman, T [1 ]
Jan, CH [1 ]
Kenyon, C [1 ]
Klaus, J [1 ]
Kuhn, K [1 ]
Ma, ZY [1 ]
Mcintyre, B [1 ]
Mistry, K [1 ]
Murthy, A [1 ]
Obradovic, B [1 ]
Nagisetty, R [1 ]
Nguyen, P [1 ]
Sivakumar, S [1 ]
Shaheed, R [1 ]
Shiften, L [1 ]
Tufts, B [1 ]
Tyagi, S [1 ]
Bohr, M [1 ]
El-Mansy, Y [1 ]
机构
[1] Intel Corp, Log Technol Dev, Hillsboro, OR 97124 USA
关键词
CMOS; metal-oxide-semiconductor field-effect transistors (MOSFETs); strained-silicon; very large scale integration (VLSI);
D O I
10.1109/TED.2004.836648
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-kappa CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si1-xGex in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by > 50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields, in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (similar to 5 X) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si1-xGex substrate approach.
引用
收藏
页码:1790 / 1797
页数:8
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