Optimizing MOS transistor mismatch

被引：47

作者：

Lovett, SJ

Welten, M

Mathewson, A

Mason, B

机构：

[1] Natl Univ Ireland Univ Coll Cork, Natl Microelect Res Ctr, Cork, Ireland

[2] GEC Plessey Semicond Ltd, Plymouth PL6 7BQ, Devon, England

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 01期

关键词：

mixed analog-digital integrated circuits; modeling; MOS devices; MOSFET's;

D O I：

10.1109/4.654947

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An investigation of MOS transistor mismatch is undertaken and a methodology is developed for optimizing mis-match without increasing layout area. Dramatic improvements of up to 300% in matching can be realized by selecting the optimum W/L ratio without changing the overall WL area product, The theoretical basis for the obtainable improvements is fully described and an expression is derived and verified by experiment to predict the W/L ratio which gives optimum matching.

引用

页码：147 / 150

页数：4

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