Effect of VLSI interconnect layout on electromigration performance

被引：19

作者：

Atakov, EM ^{[1
]}

Sriram, TS ^{[1
]}

Dunnell, D ^{[1
]}

Pizzanello, S ^{[1
]}

机构：

[1] Digital Equipment Corp, Hudson, MA 01749 USA

来源：

1998 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 36TH ANNUAL | 1998年

关键词：

D O I：

10.1109/RELPHY.1998.670668

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We characterized the reliability of multiple-via contacts, as well as the impact of the contact current direction on the failure statistics and short-length effect in Ti/Al(Cu)/Ti/TiN lines. A significant difference between the sheet resistances of the top and bottom shunting layers results in a bimodal failure time distribution for the downward electron flow direction. It also causes a significant difference in the short-length resistance saturation for the two current directions.

引用

页码：348 / 355

页数：8