A comparison of TIN processes for CVD W/TiN gate electrode on 3nm gate oxide

被引：40

作者：

Yang, H ^{[1
]}

Brown, GA ^{[1
]}

Hu, JC ^{[1
]}

Lu, JP ^{[1
]}

Kraft, R ^{[1
]}

Rotondaro, ALP ^{[1
]}

Hattangady, SV ^{[1
]}

Chen, IC ^{[1
]}

Luttmer, JD ^{[1
]}

Chapman, RA ^{[1
]}

Chen, PJ ^{[1
]}

Tsai, HL ^{[1
]}

Amirhekmat, B ^{[1
]}

Magel, LK ^{[1
]}

机构：

[1] Texas Instruments Inc, Semicond Proc & Device Ctr, Dallas, TX 75265 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650423

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

CVD W/CVD TiN stacks are studied for the first time as gate electrodes on 3nm gate oxide and compared with the CVD W/PVD (sputtering) TiN gate stacks and the baseline nf poly gate. It is found that the PVD TiN has higher metal-to-SiO2 barrier height (similar to 3.77eV) than that of the CVD TiN (3.62eV). The CVD W/PVD TiN gates without high temperature (>900C) RTP anneal show good electrical characteristics on 3nm gate oxide, and the CVD TiN is less favorable due to its high impurities. High temperature anneal cause fluorine in CVD W to diffuse and interact with the gate oxide which adversely affect the gate oxide integrity (GOI). The remote plasma nitrided gate oxide (RPNO) provides a barrier between the TiN and gate oxide, and thus prevents or reduces the F-SiO2 interaction, resulting in metal gate GOI comparable to that of poly gate. The CVD metal gate is a good candidate for the non-conventional, high aspect ratio grooved gate structures due to its good conformality.

引用

页码：459 / 462

页数：4