Sub-10-ps gate delay by reducing the current crowding effect at an extension

被引：4

作者：

Hisamoto, D ^{[1
]}

Umeda, K ^{[1
]}

Ohnishi, K ^{[1
]}

Yugami, J ^{[1
]}

Ushiyama, M ^{[1
]}

Shiba, T ^{[1
]}

机构：

[1] Hitachi Ltd, Cent Res Lab, Tokyo 185, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650363

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In short-channel CMOS devices with extension structures, current crowding was found to occur in the source extension, significantly degrading current drivability. Reducing this effect by using high-dose extensions and low parasitic capacitance provided by a localized punchthrough stopper layer produced high drivability, enabling a sub-10-ps CMOS gate delay to be attained.

引用

页码：239 / 242

页数：4