Sub 1-v 5-GHz-band up- and down-conversion mixer cores in 0.35-μ m CMOS

被引：5

作者：

Wakimoto, T ^{[1
]}

Hatano, T ^{[1
]}

Yamaguchi, C ^{[1
]}

Morimura, H ^{[1
]}

Konaka, S ^{[1
]}

机构：

[1] NTT, Lifestyle & Environm Technol Labs, Atsugi, Kanagawa 2430198, Japan

来源：

2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIC.2000.852861

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

To lower the supply voltage and reduce the power dissipation of the RF front-end of wireless communication systems, a double-balanced square-law MOSFET mixer is proposed. It is applied to up- and down-conversion mixer cores. Implemented in a 0.35- mu m CMOS process, the up-conversion mixer operates with a supply voltage of 0.5 V and the supply current of 0.8 mA in the 5-GHz band. The local leakage is suppressed below -40 dBc. The down-conversion mixer core drains 0.4 mA from 1-V supply in the same band. The conversion gain is 6 dB and IIP3 is +5 dBm.

引用

页码：98 / 99

页数：2