Fabrication and characterization of room temperature silicon single electron memory

被引:37
作者
Guo, LJ [1 ]
Leobandung, E [1 ]
Zhuang, L [1 ]
Chou, SY [1 ]
机构
[1] Univ Minnesota, Dept Elect Engn, Nanostruct Lab, Minneapolis, MN 55455 USA
来源
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B | 1997年 / 15卷 / 06期
关键词
D O I
10.1116/1.589740
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A single electron memory was demonstrated in crystalline silicon that has a transistor channel width of similar to 10 nm and a nanoscale floating gate of dimension similar to(7 nm x 7 nm x 2 nm), patterned by electron beam lithography, lift-off, and reactive ion etching. Quantized shift in the threshold voltage and self-limited charging process have been observed at room temperature. Analysis has shown that these quantized characteristics are the results of single electron charging effect in the nanoscale floating gate. (C) 1997 American Vacuum Society.
引用
收藏
页码:2840 / 2843
页数:4
相关论文
共 5 条
[1]   10-NM ELECTRON-BEAM LITHOGRAPHY AND SUB-50-NM OVERLAY USING A MODIFIED SCANNING ELECTRON-MICROSCOPE [J].
FISCHER, PB ;
CHOU, SY .
APPLIED PHYSICS LETTERS, 1993, 62 (23) :2989-2991
[2]   A silicon single-electron transistor memory operating at room temperature [J].
Guo, LJ ;
Leobandung, E ;
Chou, SY .
SCIENCE, 1997, 275 (5300) :649-651
[3]   Single electron and hole quantum dot transistors operating above 110 K [J].
Leobandung, E ;
Guo, LJ ;
Wang, Y ;
Chou, SY .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1995, 13 (06) :2865-2868
[4]   SELF-LIMITING OXIDATION FOR FABRICATING SUB-5 NM SILICON NANOWIRES [J].
LIU, HI ;
BIEGELSEN, DK ;
PONCE, FA ;
JOHNSON, NM ;
PEASE, RFW .
APPLIED PHYSICS LETTERS, 1994, 64 (11) :1383-1385
[5]   ROOM-TEMPERATURE SINGLE-ELECTRON MEMORY [J].
YANO, K ;
ISHII, T ;
HASHIMOTO, T ;
KOBAYASHI, T ;
MURAI, F ;
SEKI, K .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (09) :1628-1638