A 2.0V, 0.35μm partially depleted SOI-CMOS technology

被引：20

作者：

Mistry, K ^{[1
]}

Grula, G ^{[1
]}

Sleight, J ^{[1
]}

Bair, L ^{[1
]}

Stephany, R ^{[1
]}

Flatley, R ^{[1
]}

Skerry, P ^{[1
]}

机构：

[1] Digital Equipment Corp, Hudson, MA 01749 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650452

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 0.35 mu m SOI CMOS technology has been demonstrated with excellent partially depleted device characteristics, minimal floating body effects, a unique Schottky body tie scheme, and 1M SRAM yield approaching bulk CMOS. A state-of-the-art microprocessor fabricated on SOI showed greater than 20% performance improvement over bulk CMOS at the same V-DD, or 50% reduction in power dissipation at the same operating frequency.

引用

页码：583 / 586

页数：4