An 8Mb demonstrator for high-density 1.8V phase-change memories

被引：51

作者：

Bedeschi, F ^{[1
]}

Resta, C ^{[1
]}

Khouri, O ^{[1
]}

Buda, E ^{[1
]}

Costa, L ^{[1
]}

Ferraro, M ^{[1
]}

Pellizzer, F ^{[1
]}

Ottogalli, F ^{[1
]}

Pirovano, A ^{[1
]}

Tosi, M ^{[1
]}

Bez, R ^{[1
]}

Gastaldi, R ^{[1
]}

Casagrande, G ^{[1
]}

机构：

[1] STMicroelect, MPG & Cent R&D, I-20041 Agrate Brianza, Milano, Italy

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

10.1109/VLSIC.2004.1346644

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An 8Mb Non-Volatile Memory Demonstrator incorporating a novel 0.32 mum(2) Phase-Change Memory (PCM) cell using a Bipolar Junction Transistor (BJT) as selector and integrated into a 3V 0.18 mum CMOS technology is presented. Realistically large 4Mb tiles with a voltage regulation scheme that allows fast bitline precharge and sense are proposed. An innovative approach that minimizes the array leakage has been used to verify the feasibility of high-density PCM memories with improved Read/Write performance compared to Flash. Finally, cells distributions and first endurance measurements demonstrate the chip functionality and a good working window.

引用

页码：442 / 445

页数：4