On the thermal performance characteristics of three-dimensional multichip modules

The study explores the thermal performance of three-dimensional (3-D), vertically stacked multi-chip modules (the so-called MCM-V) in natural convection through finite element (FE) modeling and experimental validation. A modified Infrared (IR) thermography-based thermal characterization (IRTTC) technique that integrates a 3-D heat conduction FE modeling and a two-phased IR thermography measurement process is proposed. In contrast to the conventional IRTTC technique (Chen et al. [1]), the technique can improve the resolution of the captured thermal images so as to attain better characterization of the chip junction temperature. The effectiveness of the proposed modified IRTTC technique is confirmed by means of the thermal test die (TTD) measurement. Furthermore, for facilitating subsequent parametric thermal design, a direct FE approach (DFEA) is also introduced. The DFEA simply incorporates existing empirical models for heat transfer (HT) coefficients to describe the surface heat transfer to the ambient through convection and radiation in the proposed heat conduction FE model. Through the modified IRTTC technique and the TTD measurement, the validity of the proposed FE modeling, including the proposed heat conduction FE model and the applied empirical models for HT coefficients, is verified. With the validated FE modeling, four different chip stacking structures Of MCM-V packages, including the thick-die-attach, pyramid, cross and dummy-die types, are investigated. In addition, some essential design factors, affecting the thermal performance of the MCM-V, are also extensively explored through parametric FE study. Eventually, an extensive thermal design guideline is accordingly provided.