Sub-picosecond jitter SiGeBiCMOS transmit and receive PLLs for 12.5Gbaud serial data communication

被引:8
作者
Friedman, D [1 ]
Meghelli, M [1 ]
Parker, B [1 ]
Ainspan, H [1 ]
Soyuer, M [1 ]
机构
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Heights, NY 10598 USA
来源
2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2000年
关键词
D O I
10.1109/VLSIC.2000.852870
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Fully integrated SiGe BiCMOS transmit and receive PLLs for 8B/10B coded 10Gb/s serial links operate with excellent jitter characteristics. The transmit PLL (TxPLL) provides a 12.5GHz clock with 0.4ps rms jitter synthesized from a similar to 195.3MHz reference. The receive PLL (RxPLL), which exhibits <0.56ps rms jitter generation, extracts a full rate clock and recovers data from a 12.5Gb/s input bit stream. The RxPLL operates error-free when tested with a 14km optical link test bench. The power consumption of the TxPLL and RxPLL cores at 3.3V are 270mW and 330mW, respectively.
引用
收藏
页码:132 / 135
页数:4
相关论文
共 6 条
[1]  
EWEN JF, 1995, IBM J RES DEV JAN, P73
[2]  
EWEN JF, 1995, ISSCC FEB, P32
[3]   A 155-MHZ CLOCK RECOVERY DELAY-LOCKED AND PHASE-LOCKED LOOP [J].
LEE, TH ;
BULZACCHELLI, JF .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (12) :1736-1746
[4]  
Meghelli M., 1997, ECCTD '97. Proceedings of the 1997 European Conference on Circuit Theory and Design, P1366
[5]  
MEGHELLI M, 2000, ISSCC 00
[6]   A DC-BALANCED, PARTITIONED-BLOCK, 8B/10B TRANSMISSION CODE [J].
WIDMER, AX ;
FRANASZEK, PA .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1983, 27 (05) :440-451