Origin of gate hysteresis in carbon nanotube field-effect transistors

We have studied gate hysteresis of carbon nanotube field-effect transistors (CNFETs) on silicon oxide substrates in an ultrahigh vacuum (UHV) at low temperatures. It is found that the hysteresis is neither reduced by thermal annealing at temperatures over 300 C under UHV nor significantly affected by independent adsorption of ammonia or water at T = 56 K. However, the hysteresis decreases greatly upon coadsorption of water and ammonia below condensation temperatures and restores completely with desorption of the adsorbed water layer. On the basis of these results, it is concluded that the main cause of gate hysteresis in CNFETs on silicon oxide substrate is charge transfer between the carbon nanotube and charge traps at the silicon oxide/ambient interface. We propose a mechanism for gate hysteresis that involves surface silanol groups as the major sources of screening charges. This surface silanol model is supported by results from scanning surface potential microscopy (SSPM).