A high-performance 0.1μm CMOS with elevated salicide using novel Si-SEG process

被引：17

作者：

Wakabayashi, H ^{[1
]}

Yamamoto, T ^{[1
]}

Tatsumi, T ^{[1
]}

Tokunaga, K ^{[1
]}

Tamura, T ^{[1
]}

Mogami, T ^{[1
]}

Kunio, T ^{[1
]}

机构：

[1] NEC Corp Ltd, ULSI Device Dev Labs, Silicon Syst Res Labs, Kanagawa 22911, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.649473

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

High-performance 0.1 mu m CMOS devices with elevated salicide film for gate electrode and source/drain (S/D) regions and 80-nm gate side-wall have been demonstrated by a novel silicon selective epitaxial growth (SEG) process. Both junction leakage current and electrical bridging between the gate electrode and S/D regions are suppressed by this high-quality and highly-selective Si-SEG process. The elevated-salicide 0.1-mu m CMOS devices have high reliability and high drive current; and are suitable for future high-performance logic LSIs.

引用

页码：99 / 102

页数：4