A low power (45mW/latch) static 150GHz CML divider

被引：22

作者：

Hitko, DA ^{[1
]}

Hussain, T ^{[1
]}

Jensen, JF ^{[1
]}

Royter, Y ^{[1
]}

Morton, SL ^{[1
]}

Matthews, DS ^{[1
]}

Rajavel, RD ^{[1
]}

Milosavljevic, I ^{[1
]}

Fields, CH ^{[1
]}

Thomas, S ^{[1
]}

Kurdoghlian, A ^{[1
]}

Lao, ZH ^{[1
]}

Elliott, K ^{[1
]}

Sokolich, M ^{[1
]}

机构：

[1] HRL Labs LLC, Malibu, CA 90265 USA

来源：

2004 IEEE CSIC SYMPOSIUM, TECHNICAL DIGEST 2004: 26TH ANNIVERSARY: COMPOUNDING YOUR CHIPS IN MONTEREY | 2004年

关键词：

D O I：

10.1109/CSICS.2004.1392523

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Operation of a static, current mode logic (CML) frequency divider to clock frequencies exceeding 150GHz is reported. The divide-by-8 circuit described here has been realized in a highly scaled 0.4muM InP/InGaAs/InP DHBT technology, dissipates only 45m W per latch, and achieves this using purely resistive loads. Thermal limitations in device performance are observed to play a key role, demonstrating the need for aggressive heat management in high speed technologies. On a full thickness wafer in a 27degreesC ambient, the maximum operating frequency of the divider was 143.6GHz; this range extended to 151.2GHz when an air flow at -30degreesC was established across the wafer.

引用

页码：167 / 170

页数：4